1. Field of the Invention
The present invention relates to a direct memory access control technology, an information processing technology, and a program, and more specifically to an effective technology which applies to a direct memory access (DMA) technology, etc. in an information processing system which requires a high-speed data transfer.
2. Description of the Related Art
In a computer system, it is an important subject to implement data transfer effectively between memory and memory or between memory and an input/output device (I/O device) in order to improve the performance of the computer system. DMA is known as a method of solving this subject. (For example, refer to Patent Document 1)
An input/output (I/O) device transfers data to memory or receives data transferred from memory, and a storage device and an interface device are included in the I/O device. DMA is a mechanism in which dedicated hardware called a DMA control circuit controls data transfer based on instructions from a central processing unit (CPU) instead of the CPU controlling data transfer in the computer system.
In such a case, the CPU, memory and DMA control circuit are connected to one another via, for example, a memory hub, and the CPU, memory and DMA control circuit are supposed to transmit and receive data via this memory hub.
An instruction issued from the CPU to the DMA control circuit is called a descriptor, and a method by which the DMA circuit autonomously reads the descriptor from the memory and refers to the descriptor after the CPU prepares the descriptor in the memory has been widely used.
In other words, in a conventional method, apart from the data transferred by DMA to local memory under the control of the CPU, a descriptor in which control information (address of a transfer source, address of a transfer destination, transfer size, etc.) of DMA is included is developed.
When DMA is started by the CPU, the DMA circuit reads the descriptor and analyzes the control information, and transfers the data specified by the address of the transfer destination (local memory) to the I/O device by the data size designated by the descriptor.
As known from the above operation sequence, after the CPU prepares the descriptor and starts the DMA control circuit, the CPU can implement any other processing while data transfer is implemented, until DMA completion notification is provided to the CPU by an interrupt. Thus, the CPU is released from the comparatively simple process of data transfer and becomes available for more complicated processes, so that the performance of the system can be improved.
However, in the conventional DMA control technology in which a descriptor and data must be prepared separately in a memory, as described above, there are technical problems as follows.
In the case of the above conventional technology, in both “descriptor fetch” in which the DMA control circuit reads a descriptor and “data fetch” in which the DMA circuit reads data as the target of a DMA transfer, memory reading arises twice, and when reading such long data transfers that are generally implemented by DMA transfer are implemented in any interface via a memory hub, the overhead accompanied with data transfer becomes large because pre-fetch of the data is implemented in the memory hub.
Disclosed in Patent Document 1 is a technology which can change the functions of a DMA processing device by means of a program by associating each function of the DMA processing device with an instruction word, inputting a transfer processing procedure comprising an instruction word into a program storage area of the DMA processing device from outside, and implementing a transfer process in accordance with the function corresponding to the inputted instruction word, however, the aforesaid technical problems are not recognized in this technology.
Patent Document 1: Kokai (unexamined patent publication) No. 05-216808